The embodiments of the present invention relate to a semiconductor memory device performing a program operation, an operating process thereof, and a memory system including the same.
FIG. 1 is a circuit diagram for describing a program operation of a two-dimensional (2D) semiconductor memory device.
FIG. 1 illustrates a memory block including two memory strings ST1 and ST2. Each memory string includes a drain select transistor DST, memory cells C1 and C2, and a source select transistor SST, which are connected in series between bit lines BL1 and BL2 and a common source line CSL. For convenience of description, an exemplary embodiment in which a cell string includes two memory cells C1 and C2 will be described.
The device performs a program operation to store data to the memory cell C21, which is connected to a second word line WL2 and the first bit line BL1 among the memory cells included in the first string ST1. A program permission voltage (for example, 0V) is supplied to the selected first bit line BL1, and a program inhibition voltage (for example, Vcc) is supplied to the unselected second bit line BL2. A program voltage Vpgm is supplied to the selected second word line WL2, and a pass voltage Vpass is supplied to an unselected first word line WL1. A supply voltage (for example, Vcc) is supplied to the drain select transistor DST, and a ground voltage (for example, 0 V) is supplied to the source select transistor SST. In this case, a channel of the second string ST2 is precharged to a voltage level between Vcc and Vth. The channel of the second string ST2 is boosted thereafter, and thereby a memory cell C22 connected to the second word line WL2 and the second bit line BL2 is program-inhibited while the memory cell is programmed.
Recently, a three-dimensional (3D) memory device has been studied for high integration of the memory device. Since memory cells are arranged in a three-dimensional array in the three-dimensional memory device, there are differences between the three-dimensional memory device and the two-dimensional memory device in terms of operation characteristics.
Accordingly, the operation needs to be adjusted to accommodate the operation characteristics of the three-dimensional memory device.